Advances in semiconductor manufacturing technology have resulted in, among other things, reducing the cost of sophisticated electronics to the extent that integrated circuits have become ubiquitous in the modern environment.
As is well-known, it is common to manufacture integrated circuits, on roughly circular semiconductor substrates, or wafers. Further, it is common to form such integrated circuits so that conductive regions disposed on, or close to, the uppermost layers of the integrated circuits are available to act as terminals for connection to various electrical elements disposed in, or on, the lower layers of those integrated circuits. In testing, these conductive regions are conventionally contacted with a probe card to determine if the integrated circuits on the wafer are capable of operating according to predetermined specifications.
A typical process of wafer level testing, sometimes referred to as wafer sort, includes connecting one or more integrated circuits, or dice, with a test apparatus by means of a probe card that electrically contacts those integrated circuits on a wafer. A probe card might typically contact four die at a time as it steps across the wafer, each contact pass being known in the art as a touch-down. Thus a 300 mm wafer containing 1,200 die would receive 300 touch-downs during a wafer sort sequence. Using existing wafer sort methods and apparatus, such a sequence would typically engage the wafer for several hours.
One type of wafer-level testing is known as functional testing. Functional testing exercises an integrated circuit at its device pins and observes the performance of the integrated circuit at the devices pins. As integrated circuits have become more complex, and their logic gates have become more deeply embedded, comprehensive functional testing has consequently become more difficult because of the tremendous number of states and state transitions needed for exhaustive fault coverage. To address these testing problems, a design methodology, sometimes referred to as Design For Testability (DFT), came into wide use, and in which additional circuitry, unrelated to the specified functionality of an integrated circuit, is added thereto in a such a manner that the deeply embedded logic gates can be reached and exercised. This approach is sometimes referred to as structural testing because it focuses on determining whether the constituent parts of an integrated circuit can be properly operated rather than whether the integrated circuit as a whole, and viewed from the device pins, achieves a specified functionality. In a related approach, circuitry is added to an integrated circuit that actually exercises and records the performance of portions of the integrated circuit, rather than driving the internal circuitry entirely with stimuli provided by a signal source external to the integrated circuit. This approach is sometimes referred to as Built-In Self-Test (BIST). BIST allows the results of internal test operations to be reported to an external tester. In many instances BIST allows for the communication of the results of the internal test operations without the requirement for the use of all of the device pins of the integrated circuit.
In some circumstances it is desirable to test an integrated circuit in some combination of functional, structural, and BIST test sequences. Unfortunately, conventional testing apparatus and methods result in such separate tests being performed sequentially, and often with different physical arrangements of test apparatus.
What is needed are methods and apparatus for providing simultaneous access to the integrated circuits of a wafer for concurrently performing two or more types of testing, for example two or more of functional, structural, and BIST testing.